

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

--具有三级时钟延迟的电路设计 --
--实际电路中信号的延迟是通过触发器对信号的传递实现的

entity c5_delay is
port (
    a, clk : in std_logic;
    q1, q2, q3 : out std_logic
);
end c5_delay;

architecture Behavioral of c5_delay is
    signal qn1, qn2, qn3 : std_logic;
begin
    process(clk) begin
        if clk'event and clk = '1' then
            qn1 <= a;
            qn2 <= qn1;
            qn3 <= qn2;
        end if;
    end process;
    
    q3 <= qn3;
    q2 <= qn2;
    q1 <= qn1;

end Behavioral;






--------
-- 仿真
--------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity c5_delay_test is
--  Port ( );
end c5_delay_test;

architecture Behavioral of c5_delay_test is

    signal a, clk : std_logic;
    signal q1, q2, q3 : std_logic;
    
    component c5_delay
    port (
        a, clk : in std_logic;
        q1, q2, q3 : out std_logic
    );
    end component;
    
begin
    d1 : c5_delay port map (
        a => a, clk => clk, q1 => q1, q2 => q2, q3 => q3
    );

    process begin
        a <= '0'; wait for 40ns;
        a <= '1'; wait for 40ns;
        a <= '0'; wait;
    end process;
    
    process begin
        clk <= '0'; wait for 10ns;
        clk <= '1'; wait for 10ns;
    end process;

end Behavioral;
